1. Field of the Invention
The present invention relates generally to semiconductor random access memory devices, and more particularly to a multi-level phase change random access memory device with each storage node storing multiple bits.
2. Background of the Invention
A phase change random access memory (PRAM) device is a kind of non-volatile memory device, similar to a flash memory device, a ferroelectric random access memory (FeRAM) device, and a magnetic random access memory (MRAM) device. The PRAM device uses a phase change material as a data storage layer with a difference between the resistances of an amorphous phase and a crystalline phase of the phase change material indicating a state of a data bit.
For example, a conventional phase change material, such as a Ge—Sb—Te-based material, has a much higher resistance in an amorphous phase than in a crystalline phase. A phase transformation between such amorphous and crystalline phases is performed by Joule heating generated by a current conducted through the phase change material.
For example, when a predetermined voltage is applied to the phase change material for a short period of time, a portion of the phase change material is heated above a crystallization temperature and then is rapidly cooled to be in an amorphous state. Alternatively, when the predetermined voltage is applied to the phase change material in the amorphous state for a relatively long period of time, the phase change material is transformed back into the crystalline phase.
In the conventional PRAM device, the phase transformation from the amorphous phase to the crystalline phase is defined as a set operation, and the applied voltage used for such a transformation is referred to as a set voltage. Conversely, the phase transformation from the crystalline phase to the amorphous phase is defined as a reset operation, and the applied voltage used for such a transformation is referred to as a reset voltage.
However, a phase change material in the conventional PRAM device is in only a single set state and a single reset state with the phase change material layer storing only the two possible states of 1-bit data.